1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, particularly, a structure of a buried layer of a Bi-CMOS device in which a bipolar transistor and a CMOS transistor are formed in one and same substrate.
2. Prior Art Description
FIG. 6 is a cross section of a conventional Bi-CMOS device when P.sup.+ type buried layers and N.sup.+ type buried layers are formed by using the self alignment.
The device has a structure in which the N.sup.+ type buried layers 3 and the P.sup.+ type buried layers 4 are formed in contact with each other in a P type silicon substrate 1 and below an N type epitaxial layer 5.
In a portion of the N type epitaxial layer 5 on the N.sup.+ type buried layer 3, an N well region 6 is formed in which a P channel insulating gate field effect transistor (referred to as "MOS transistor", hereinafter) is formed and, in a portion of the N type epitaxial layer 5 on the P.sup.+ type buried layers 4, a P well region 7 is formed in which an insulating region of the bipolar transistor and the N channel MOS transistor are formed.
Further, in another portion of the N type epitaxial layer 5 on the N.sup.+ type buried layers 3, there is neither N type well 6 nor P type well 7 formed, resulting in an NPN bipolar transistor. Further, an N channel MOS transistor and a P channel MOS transistor are formed by forming a field insulating film 8, a gate oxide film 9, a gate electrode 10 of the N channel MOS transistor, a gate electrode 11 of the P channel MOS transistor, an N channel source.cndot.drain region 13 and a P channel source.cndot.drain region 14.
Further, an N.sup.+ type collector lead region 12, an external base region 15, a base region 16 and an emitter region 17 of the NPN bipolar transistor are formed.
The P.sup.+ type buried layer 4 surrounding the NPN transistor and the P type well region 7 thereof have a role of electrically separating the NPN bipolar transistor from others.
An usual manufacturing method of this integrated circuit device will be described with reference to FIGS. 7(a) to 7(f).
As shown in FIG. 7(a), a silicon oxide film 2 is grown on the P type silicon substrate 1 to a thickness of 30 to 100 nm and is then patterned by using the photolithography. Then, as shown in FIG. 7(b), an N type impurity such as arsenide is ion-injected to the silicon substrate 1 through the patterned silicon oxide film 2 as a mask under conditions of injecting energy of 40 to 80 keV and dose of 5.times.10.sup.14 to 5.times.10.sup.15 cm.sup.-2. Thereafter, the wafer is heat treated in oxygen atmosphere at a temperature as high as 1000.degree. C. to 1200.degree. C. for 2 to 4 hours to immigrate arsenide into the P type silicon substrate 1. Thus, the region containing N type impurity at high density is rapidly oxidized, resulting in a thick silicon oxide film.
Then, the thermal oxide film 2 used as the mask is removed by wet etching. Thus, a pattern 301 of the N.sup.+ type buried layer 3 is formed on the P type silicon substrate 1.
Then, as shown in FIG. 7(c), a P type impurity such as boron is ion injected to a whole surface of the substrate 1 under conditions of injecting energy of 80 to 120 keV and dose of 1.times.10.sup.13 to 5.times.10.sup.13 cm .sup.-2. Thereafter, the N.sup.+ type buried layers 3 and the P.sup.+ type buried layers 4 are formed by epitaxially growing the N type epitaxial layer 5 to a thickness of 0.8 to 1.2 .mu.m.
Then, as shown in FIG. 7(d), the P well region 7 is formed by ion-injecting an impurity such as boron with using a photo resist 18 having an opening 18A as a mask.
Then, as shown in FIG. 7(e), the N well region 6 is formed by ion-injecting an impurity such as phosphor with using a photo resist 19 having an opening 19A as a mask.
Thereafter, the field insulating layer 8 is formed by using the known preferential thermal oxidation, as shown in FIG. 7(f).
In the conventional bi-CMOS device having the N.sup.+ type buried layers 3 and the P.sup.+ type buried layers 4 in contact with the buried layers 3, there is a merit that the N.sup.+ type buried layers 3 and the P.sup.+ type buried layers 4 can be made contact with each other simply in a single lithographic step.
However, since the N.sup.+ type buried layers 3 and the P.sup.+ type buried layers 4 are in contact with each other, there is a problem that it is impossible to reduce an area required for insulating separation of the bipolar transistor.
FIG. 8 is a cross section of a region of the substrate in which bipolar transistors are arranged adjacent to each other and is useful to understand this problem.
In FIG. 8, X denotes a distance between the N.sup.+ type buried layers 3, that is, a width of the P.sup.+ type buried layer which corresponds to a width of the P well and Y denotes a distance between the external base region and the well region of the bipolar transistor. Therefore, the distance required to insulating and separating the bipolar transistor is X+2Y.
As a matter of convenience, leak-paths in the P well region, in the P.sup.+ type buried layer 4, between the P well region 7 and the P.sup.+ type external base region 15 and between the P.sup.+ type buried layer 4 and the P.sup.+ type external base region 15 are denoted by "a", "b", "c" and "d", respectively.
The value of X is determined by a punch-through between the N type epitaxial regions formed on both sides of the P well region or between the N.sup.+ type buried layers formed on both sides of the P.sup.+ type buried layer, that is, "a" or "b".
Since the impurity density of the N.sup.+ type buried layer is generally higher than that of the N type epitaxial layer, the value of X is determined by "b".
On the other hand, the value of Y is determined by a punch-through between the external base region and the P well region or between the P.sup.+ type buried layers, that is, "c" or "d". Leakage in "c" is the punch-through between the external base region having relatively high impurity density and the P well region and leakage in "d" is due to a rise out of the impurity from the P.sup.+ type buried layer after the heat treatment step of the manufacturing steps of the device.
Although there is a dependency on the impurity density settings in various portions of the device, "c" is generally predominant over "d". Since, therefore, it is necessary to provide enough distances for both "b" and "c", it is impossible to reduce the width of the element separating region and thus it is impossible to improve the integration density of the semiconductor integrated circuit device.